1. Retain the exact marking and ordered identity
A package marking that differs from an order record creates an identification question, not an immediate answer about the device. Preserve both strings as they appear and state which came from the physical package and which from the purchasing record. A seller should not silently replace one with the other merely to produce a shorter FPGA description for released inventory.
Lattice's dual-marking FAQ describes some devices whose stamped identification looks like a combination of entries in the datasheet. That documented possibility gives the reviewer a reason to investigate the applicable family context. It does not establish that every mismatch is a legitimate dual mark or identify an unknown seller's device. Keep incomplete or conflicting readings visible until the relevant product records explain them.
Retain the product family and available ordering identity alongside the observed stamp. A board name, firmware label or internal project reference can help locate records, but it addresses a different object. The enquiry should distinguish the silicon identification from the assembly and its configuration. This prevents a programme nickname from acquiring an unsupported speed or temperature meaning during stock consolidation.
2. Use family-specific speed/temperature context
The Lattice FAQ explains that a dual marking can concern speed grade, operating temperature or both. It discusses older and newer device families differently. Preserve that qualification when summarising the concept. The fact that a manufacturer documents one dual-mark relationship does not provide a universal algorithm for reading the suffix of every FPGA from that manufacturer or another supplier.
In its older-family discussion, the FAQ relates commercial and industrial performance descriptions. In its newer-family discussion, it explains the dual mark through the operating-temperature context and separately addresses operation under the user's design conditions. This guide retains those distinctions qualitatively. It supplies no grade numbers, temperature limits, ordering-table reconstruction or claim that an offered device satisfies a newly inferred specification.
The FAQ points readers to the corresponding datasheet's ordering information or part-number description. Keep an exact reference where available and state when that interpretation has not been resolved. Do not fill the gap from a nearby family or an unread table. A photograph and a documented explanation remain different records: one preserves the observed characters, while the other supports what those characters mean.
3. Separate grade from user-design timing
A speed-grade description is not a measured clock rate for a customer's implemented design. Lattice's newer-family discussion directs speed under user conditions to FPGA design-tool context, naming its tools. The stock description should retain the supported grade without treating that label as a completed timing result for a board, configuration or design that has not been identified and evaluated.
Where an existing design report is available, retain its actual device reference, design revision and stated scope separately. A report on one configuration should not become a performance claim for all surplus devices with similar markings. Conversely, a clear device-grade interpretation does not supply a missing implementation report. The recipient needs to know whether the evidence identifies the semiconductor or concerns a particular design using it.
Keep temperature descriptions within the applicable family explanation as well. A dual-mark interpretation does not document where a removed device operated or its current condition. No timing tool has been run for this enquiry, and no maximum clock or temperature guarantee is provided. The useful result is a bounded identity description with the remaining design questions still attached to their own evidence.
4. Offer grade-identified FPGA groups
Separate groups whose dual markings have an applicable interpretation from those still needing exact-family records. Preserve the observed characters even when an interpreted field is added. That allows another reviewer to revisit the conclusion without losing the original reading. A common family heading should not conceal that only certain identified devices have matching order or marking explanations.
For an ICULTRA FPGA enquiry, provide those linked identification records and state which speed or temperature interpretations remain unresolved. Programming and protection history belong in separate disclosures covered by the MCU-state guide; they do not establish silicon grade. This preparation reports no timing closure, electrical test or qualification, and does not promise acceptance. Any evaluation scope and purchase terms must concern the actual identified material.
Sources and further reading
Lattice FAQ364 supports only the qualitative, family-dependent dual-mark discussion and its documentation boundaries. No numeric grade decoding, ordering-table interpretation, timing result or operating-temperature guarantee is supplied.