Separate the PMA lane from the fabric-facing PCS
The physical-medium attachment, or PMA, is one part of the embedded transceiver rather than the entire fabric interface. Microchip's PolarFire guide assigns the PMA serial-to-parallel and parallel-to-serial conversion responsibilities along with its receive and transmit functions. The PCS provides a separate connection toward the FPGA fabric. A transceiver lane therefore contains related functional layers, not one interchangeable signal path label.
On reception, the guide describes an input buffer, clock-and-data recovery and a deserializer within the PMA. The resulting parallel data proceeds through the PMA-to-PCS interface toward the fabric-facing logic. This sequence identifies where the serial representation becomes a parallel one and where the next layer begins. It does not say that conversion alone has completed decoding or established a protocol's interpretation of that data.
This embedded architecture is also different from an external pluggable optical module. A family capability statement does not identify an offered module, a physical lane count or the product programmed into a particular FPGA. Keep the PMA and PCS responsibilities explicit without deriving pins, rates or SKU features from the broad transceiver-enabled description.
Distinguish reference locking from recovering the received data clock
The receive CDR can relate its clock to different references in the named PolarFire account. Lock-to-reference follows the receiver's reference clock. Lock-to-data instead follows transitions in the incoming serial stream to recover the timing needed for reception. Both involve the receive clock system, but they do not describe the same relationship to the received information.
Microchip explains that the reference mode tracks the reference through its phase-frequency detector, while the data mode uses the incoming stream's phase relationship in controlling the receive oscillator. The deserializer works closely with this clock recovery. Retaining which timing source is being followed makes the condition more informative than an unqualified assertion that the receiver is locked.
A reference-related condition consequently should not be treated as proof that timing has been recovered from incoming data. The guide also retains data-transition context for the acquisition of lock, rather than supplying one unconditional duration. This account adopts no lock time, status recipe or mode-setting sequence. It describes the distinction between local reference timing and recovered data timing without claiming that an actual offered FPGA has received or decoded a stream.
Keep PCS coding mode separate from serial transport
The PCS contributes functions beyond transporting serial information through the PMA. Microchip lists named alternatives involving coding, gearing and fabric interfaces, while PMA-only operation provides access without encoding or decoding. The physical serial hardware therefore does not establish which of these additional functions a particular design uses. A transceiver-enabled family label leaves that implementation question open.
The guide describes its 8b10b transcoder as protocol independent. Encoding and decoding support at that layer consequently is not a complete protocol implementation. The same account distinguishes word-alignment responsibilities and the protocol-specific state or monitoring that may be needed around them. A coding-mode name should retain this functional boundary instead of being expanded into compatibility with every system using similar serial terminology.
Preserve the documented PCS alternative alongside the PMA description, without treating a supported mode as a readback of implemented logic. This separation also avoids using a speed-grade or temperature marking to infer coding state. No code pattern, data-rate equation, fabric ownership or configuration history is supplied here. The named mode explains an architectural capability and its limits, rather than establishing that an offered device contains a complete working communications design.
Separate symbol alignment from clock recovery and protocol completion
A serial clock does not by itself identify where parallel symbols begin. Microchip's 8b10b account separately describes comma detection and word alignment before incoming encoded data can be interpreted correctly as parallel information. Clock recovery concerns timing of the incoming stream; alignment concerns the grouping boundary applied to that stream. These are different responsibilities even though both are required by the receive path.
The guide expressly notes that the word aligner can select an incorrect alignment, with disparity errors or code violations appearing at the decoder. An alignment indication therefore needs interpretation within the relevant coding and protocol context. Recovering timing or finding a candidate boundary is not equivalent to demonstrating that every received word is correctly aligned and meaningful.
Protocol-specific monitoring adds another layer to the account, because the protocol determines how those errors are used in managing alignment. This explanation preserves that dependency without supplying reset actions, signal names, bit-slip instructions or a recovery sequence. It also establishes no present lock, aligned traffic, protocol compliance or link success for an offered FPGA. Conversion, clock recovery, coding and symbol boundaries remain separate functions requiring their own appropriate evidence.
Sources and further reading
Microchip PolarFire Family Transceiver User Guide DS00004164L,2026: bounded PMA/CDR/PCS/alignment prose on physical pages 8,11–12 and 27–28. The filename VB is not the internal revision. Figures, tables, numerical timing, reset procedures and present configuration/protocol claims are excluded.