Specifying a Delta-Sigma ADC's Digital Filter Latency

1. Separate output interval from conversion latency

A measurement requirement may need regularly spaced results, a prompt first settled result after a change, or both. These are different timing objectives. TI's terminology distinguishes the conversion period from conversion latency: latency concerns the time needed to produce settled output and can include multiple periods or additional processing. A rate headline alone cannot identify all those contributions.

The distinction is especially useful when comparing continuous observation with measurements that repeatedly change inputs or conditions. After an established input has been observed for a while, successive outputs can arrive at a regular interval. That interval need not describe the wait following a new input condition. Treating the two as interchangeable can leave the actual measurement task unspecified.

Conversion latency also assumes a settled analog input in TI's definition. This matters because waiting for an analog source to settle and waiting for the digital result to become settled are separate parts of the question. A statement about one does not automatically include the other. Identify which starting condition the timing evidence uses before applying it to a changed measurement.

2. Explain why filter history survives an input change

A delta-sigma converter's digital filtering uses information collected over time. An input change does not necessarily remove the information already in that filtering process. TI explains that a result following a change can therefore combine earlier and later input information. The existence of a newly calculated result does not establish that it represents only the new settled condition.

This filter history explains why the first settled result can require a different wait from subsequent outputs. Once the filter is operating on the established condition, later results can become available at the ordinary conversion interval under the described conditions. The initial wait and continuing output cadence have different roles, even though both may be presented near one another in an ADC timing discussion.

The change event itself also matters. TI distinguishes a change aligned with a conversion boundary from a change occurring during conversion, because sampled information can straddle the transition. This is a reason to identify the measurement event precisely, not a universal rule for how many samples to discard. The applicable filter and operating mode must provide the actual timing basis.

3. Read what the device hides or reports

Some ADC operations alert the device that a new measurement condition is being established. TI describes ADS124S08 behavior in which particular recognised actions restart filtering and the device withholds unsettled data before indicating a result. This is a device-specific treatment of the event. It should not be generalized into a statement that every delta-sigma data-ready indication means the filter is settled.

The application note contrasts that treatment with a mode of ADS1258 that reports new conversion results even when they are unsettled. The comparison shows why the device and mode must remain attached to the description. A familiar data-ready name cannot, by itself, tell a reader which information has been suppressed or whether a reported value meets the application's settled-result requirement.

An external input step creates another distinction: it need not be an action the converter recognises as a change event. TI also identifies changes made by an external multiplexer as outside the converter's automatic awareness. Preserve that internal-versus-external distinction when asking what the device hides. This guide does not turn it into a restart procedure or a firmware sequence. Thus two measurements using a similar filter description can still have different settling questions if one follows a recognised internal action and the other follows an external change. Identify that distinction before applying a general first-result description.

4. Translate the measurement sequence into a timing question

Describe the measurement sequence through its meaningful events. Identify what changes, whether the ADC recognises that change, and whether the requirement concerns the first settled result or later continuous results. These questions give engineering a focused timing problem. They are more useful than an unqualified conversion-time request that leaves the start condition and result meaning unspecified.

Keep architecture, acquisition and clock-jitter decisions separate. Architecture concerns the relationship between channel observations; SAR acquisition concerns analog input settling within an acquisition window; jitter concerns uncertainty in the capture instant. Filter latency addresses how time history contributes to the reported result. Shared ADC timing terminology does not make the evidence for these mechanisms interchangeable.

For the proposed delta-sigma device, request the filter, mode and recognised-event evidence applicable to the actual task. Any complete channel or system-cycle assessment must include its own application conditions. No scan-time calculation or universal sample-discard count is provided here. The central selection question is whether the available timing description identifies when the required settled measurement becomes available.

Sources and further reading

• Texas Instruments SBAA535A — Calculating Conversion Latency and System Cycle Time for Delta-Sigma ADCs

TI SBAA535A physical pages 3–4, 7 and 10–12 were reread as saved text on 15 October 2026. Timing vocabulary, filter-history prose and device-specific unsettled-data treatment are used; no plots, numerical latency, programming instructions or scan-time calculation are supplied.